AI Is Rewriting the Rules of Semiconductor Competition: From the Chip Race to a Battle for “Learning Speed”

AI is reshaping the rules of innovation in the semiconductor industry. As demand for computing performance, memory bandwidth, and parallel processing continues to surge, transistor scaling alone is no longer sufficient to deliver significant performance gains. Innovation is expanding beyond individual chips toward system-level integration, in which logic, memory, advanced packaging, and high-speed interconnects advance together.

Ahmad Khan, president of the Semiconductor Products and Customer Group at KLA, noted during his presentation at the SEMICON Taiwan CEO Summit that Moore's Law remains important, but AI is changing how semiconductor innovation takes place. Chips can no longer operate in isolation. While the industry continues to pursue smaller chip feature sizes, it must also address the challenge of improving overall system performance.

AI Redefines What Constitutes a “Chip”

As demand for AI computing power continues to rise, semiconductor technologies are evolving in parallel. Technologies such as gate-all-around (GAA) transistors, backside power delivery, complementary field-effect transistors (CFETs), high-bandwidth memory (HBM), 3D DRAM, and hybrid bonding are all advancing rapidly.

In the future, a “chip” will no longer refer simply to a single die. Instead, it will be a multi-chip system built by integrating several components through advanced packaging and high-speed interconnect technologies.

For example, a GPU may feature an advanced process node, a three-dimensional transistor architecture, and a very large die size. HBM, meanwhile, consists of multiple stacked DRAM dies and a precisely engineered logic base die. These components are integrated onto a silicon interposer through complex advanced packaging processes and connected using high-speed interconnects.

As the level of integration increases, a problem at any stage can affect the final product. Taiwan's semiconductor ecosystem—which spans logic and memory manufacturing, IC design, advanced packaging, wafer fabrication, and photomask production—has therefore become an important environment for advancing system-level integration.

Increasing system complexity also makes yield management more challenging. Ahmad Khan illustrated this with an example: if a wafer can produce 1,000 chips, a single yield-critical defect has a relatively limited impact on overall yield. However, for an extremely large chip such as an advanced GPU, a wafer may produce only five dies. If one die contains a defect, the resulting yield loss is substantially greater.

When multiple DRAM dies are stacked to form HBM, integrated with a GPU on a silicon interposer, and then connected to an IC substrate, a problem at any stage can jeopardize the manufacturing value accumulated in earlier stages. The larger the dies, the more chips contained in the package, and the more complex the integration, the greater the cost of each defect.

Hidden Defects Buried in Massive Volumes of Data

Beyond yield, reliability presents another major challenge. Ahmad Khan pointed out that GPUs, TPUs, and HBM often need to operate for extended periods during AI training and inference. As a result, in addition to yield-critical defects that directly cause product failure, the industry must pay greater attention to latent defects.

These defects may not cause immediate failures when manufacturing is completed, but can gradually emerge after prolonged operation under heavy workloads.

This makes inspection and metrology increasingly important in the AI era. Ahmad Khan described KLA's equipment as a highly sophisticated, highly automated microscope combined with a high-performance computing platform.

For example, a broadband plasma optical defect inspection system can generate approximately 125 terabytes of data per hour, or nearly 3 petabytes per day. The system must process every pixel in real time to identify abnormalities that could genuinely affect chip performance amid this enormous volume of data.

To handle these inspection workloads, KLA uses hardware such as GPU-based high-performance computing platforms, combined with AI models and physics-based algorithms, to filter massive datasets and identify defects that warrant attention.

This creates an interesting feedback loop: AI is increasing the complexity of chips and manufacturing processes, while also becoming an essential tool for detecting problems in semiconductor manufacturing through massive amounts of data.

However, more data does not automatically translate into greater manufacturing efficiency. The real challenge is turning more data into “richer information”—identifying signals that genuinely affect yield and using those insights to improve manufacturing processes.

AI Chip Yield Depends on Greater Supply Chain Collaboration

Identifying a problem is only the first step. As AI chips move toward system-level integration, with GPUs, memory, silicon interposers, and advanced packaging all closely interconnected, yield is no longer determined by any single process or manufacturing stage.

Ahmad Khan emphasized: “The final yield is the sum of all the parts.”

Even if front-end logic and memory manufacturing maintain high yields, problems during memory stacking, heterogeneous integration and packaging, or other downstream processes can still prevent the final product from meeting requirements.

This means that as AI chip integration becomes increasingly complex, every stage must share more information and identify problems earlier. Deeper collaboration across the supply chain—from design and wafer and photomask manufacturing to logic and memory production and advanced packaging—has become essential to improving final yield.

The Key to Next-Generation Innovation: “Learning Speed”

As chips move toward system-level integration, the challenges now extend beyond yield-critical defects to latent defects, while yield management has expanded from individual manufacturing processes to the entire supply chain. The standards by which the semiconductor industry measures innovation are changing accordingly.

Ahmad Khan believes that the next stage of innovation will not be determined solely by who develops individual semiconductor technologies first. More importantly, the entire semiconductor ecosystem must be able to translate Faster Innovation, Richer Information, and Deeper Collaboration into greater “Learning Velocity.”

What truly sets companies apart is not simply who identifies challenges first, but who can understand those challenges more quickly, implement corrective actions, and apply the lessons learned to the next round of technology development. As technology continues to evolve at an accelerating pace, the ability to “learn faster” is becoming a new competitive advantage for the semiconductor industry in the AI era and will be a key driver of industry innovation over the next decade.

Source of Information: TechNews